Achronix Speedster22i sBus Bedienungsanleitung

UG047, October 24, 2013 1 Speedster22i sBus Interface User Guide UG047, October 24, 2013

10 UG047, October 24, 2013 Operation The sBus takes serial data from the FPGA fabric sBus control logic (“Fabric”) and transmits it over a 2-bit d

UG047, October 24, 2013 11 Chapter 2 – sBus Functional Description In this chapter, you will learn the following about the sBus serial bus: Port List

12 UG047, October 24, 2013 6. Assert the o_sbus_ack signal, when data is ready. 7. Transmit the serial data on the o_sbus_data[1:0] signal

UG047, October 24, 2013 13 Write Operation 32-bit Data-width Mode For a 32-bit data-width mode write operation, you must do the following. 1. Assert

14 UG047, October 24, 2013 Figure 6: 8-bit Data Width sBus Write Operation

UG047, October 24, 2013 15 Chapter 3 – sBus Interfaces In this chapter, you will learn the following about the sBus serial bus: Master Interface Slave

16 UG047, October 24, 2013 FabricsBus Port Control Logicsbus_clkreset_sbus_clki_sbus_reqi_sbus_data [1:0]o_sbus_acko_sbus_data [1:0]Slave 1Slave 2

UG047, October 24, 2013 17 Chapter 4 – sBus Master Implementation In this chapter, you will learn the following about the sBus serial bus: Single Mast

18 UG047, October 24, 2013 3. Monitor the o_sbus_ack signal from the PLL sBus slave signaling the end of the write request. Note: Y

UG047, October 24, 2013 19 before a specific action, you must also consider latencies in the design to ensure that the delay from the s

2 UG047, October 24, 2013 Copyright Info Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademar

20 UG047, October 24, 2013 Chapter 5 – sBus Design Examples In this chapter, you will learn the following about the sBus serial bus: sBus Master De

UG047, October 24, 2013 21 Signal Direction Description interface (from slave) o_sbus_data[1:0] Output Output serial data of sBus interface (to slave)

22 UG047, October 24, 2013 sBus Master Operation The sBus master will move from the ST_SBUS_IDLE to the ST_SBUS_ADDR state when you assert the i_s

UG047, October 24, 2013 23 Appendix A – sBus Master Verilog Code // // Module Name : sbus_master_if // // Description : SBUS master module to transfer

24 UG047, October 24, 2013 parameter ST_SBUS_ADDR = 5'b00010; parameter ST_SBUS_WR_DATA = 5'b00100; parameter ST_SBUS_

UG047, October 24, 2013 25 sbus_cs <= ST_SBUS_WR_DATA; end ST_SBUS_WR : begin

26 UG047, October 24, 2013 if ((sbus_cs[3] && i_sbus_ack) || (sbus_cs[4] && (&rdwr_data_cnt))) o_reg_rdwr_v

UG047, October 24, 2013 27 Appendix B – Revision History The following table lists the revision history of this document. Date Version Revisions 10/24

UG047, October 24, 2013 3 Table of Contents Copyright Info ...

4 UG047, October 24, 2013 Read Operation ...

UG047, October 24, 2013 5 List of Figures Figure 1: The HD1000 FPGA with sBus interfaces ...

6 UG047, October 24, 2013 List of Tables Table 1: HD1000 sBus Port Definition ...

UG047, October 24, 2013 7 Preface About this Guide The Achronix sBus is a serial bus implemented on the AC22IHD1000-F53C3 FPGA device to allow users

8 UG047, October 24, 2013 Conventions used in this Guide This document uses the conventions shown in the following table. Item Format Examples Com

UG047, October 24, 2013 9 Chapter 1 – sBus Overview In this chapter, you will learn the following about the sBus serial bus: Introduction Operation Fe