
UG033, December 18, 2013
The startup sequence consists of sequentially asserting a number of signals to ensure proper
operation during user mode. These events are highlighted in Table 2 below.
Table 2: Startup Sequence Events
Assert Global Clock Enable
Assert Global Reset Enable
Assert Global Core Enable
The shutdown sequence is very similar in nature to the startup sequence and essentially
entails deasserting these same signals in reverse order.
User Mode: Once the device enters user mode, the design has been fully programmed
and the user can start sending and receiving data to/from the FPGA and performing intended
operations.
Kommentare zu diesen Handbüchern