UG042, August 19, 2014
Pin Connection Guidelines
Please see the table below on guidelines for connecting all IOs on the Speedster22i HD FPGAs. For completeness, debug I/Os that
have no user functionality have also been included and are indicated by a grey background.
12.75 Gbps SerDes (64 lanes)
PAD_TE_I_BCK_REF_P/M_LNUM[31:0]
The 12.75 Gbps SerDes reference clock supplied from either a
single-ended or differential external source. There is 1
differential pair for each of 2, 12.75Gbps lane.
Connect these clocks for all SerDes lanes
used in the interface. Unused clocks should
be tied to their own individual GND via a
50Ω +/- 1% termination resistor.
Note: For PCIe Gen3 operation when using
the hard PCIe controller, reference clocks
for all 8 SerDes lanes need to be connected
regardless of the data width implemented.
PAD_TE_I_BA_RX_P/M_LNUM[31:0]
Receive differential inputs to the 12.75 Gbps SerDes. One pair
for each lane.
Connect all unused receive pins directly to
GND via a 50Ω +/- 1% termination resistor.
PAD_TE_O_BA_APROBE_LNUM[31:0]
The 12.75 Gbps SerDes Analog DC test pad used internally for
debug and testing, one for each lane.
PAD_TE_O_BA_TX_P/M_LNUM[31:0]
Transmit differential outputs from the 12.75 Gbps SerDes.
There is one differential pair per each 12.75Gbps lane.
These pins should be AC coupled. Leave all
unused transmit pins unconnected.
PAD_BE_I_BCK_REF_P/M_LNUM[31:0]
The 12.75 Gbps SerDes reference clock supplied from either a
single-ended or differential external source. There is 1
differential pair for each of 2, 12.75Gbps lane.
Connect these clocks for all SerDes lanes
used in the interface. Unused clocks should
be tied to their own individual GND via a
50Ω +/- 1% termination resistor.
Note: For PCIe Gen3 operation when using
the hard PCIe controller, reference clocks
for all 8 SerDes lanes need to be connected
regardless of the data width implemented.
PAD_BE_I_BA_RX_P/M_LNUM[31:0]
Receive differential inputs to the 12.75 Gbps SerDes. One pair
for each lane.
Connect all unused receive pins directly to
GND via a 50Ω +/- 1% termination resistor.
PAD_BE_O_BA_APROBE_LNUM[31:0]
The 12.75 Gbps SerDes Analog DC test pad used for ATE and
bench testing, one for each lane
PAD_BE_O_BA_TX_P/M_LNUM[31:0]
Transmit differential outputs from the 12.75 Gbps SerDes.
There is one differential pair per each 12.75Gbps lane.
These pins should be AC coupled. Leave all
unused transmit pins unconnected.
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