Achronix Speedster22i SerDes Bedienungsanleitung Seite 89
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Overview of the modification: With respect to the steps followed in creating
simple_serdes_design, the following modifications are made in preparing
simple_serdes_design_efifo:
1. Changes in using ACE GUI during wrapper generation.
2. Changes in RTL code related to using clock signals generated by SerDes.
3. Changes in ace_placement.pdc and ace_constraint.sdc related to using clock signals from
SerDes.
These modifications are detailed below.
Modification – 1 (ACE GUI): In the design discussed above (simple_serdes_design), clock
compensation (EFIFO) was disabled. For the current derivative of the design
simple_serdes_design_efifo, EFIFO is enabled.
We will start by creating a new ACXIP file in the ACE GUI for the modified design,
simple_serdes_design_efifo. All fields in the GUI can be set to the same values as was done for
simple_serdes_design, wit hthe exception of the RX PCS Setings as shown below. The entry
fields and the available options are listed in “Table 21: Modifications for
simple_serdes_design_efifo (RX PCS Settings)” This table also presents the choices that are
made for the current design: simple_serdes_design_efifo.
Table 21: Modifications for simple_serdes_design_efifo (RX PCS Settings)
Entry field
Available Options
Choice made
Decoder
*3
•
Disabled
• 8b/10v
•
128/130b
8B10B (8b/10b) decoder
Polarity Bit Reversal (PBR)
Functions
PBR Block
*3
• PBR0
• PBR1
PBR0 (Default)
Receive Symbol Swap
*3
•
True
•
False
False
Receive Bit Order Reverse
*3
•
True
•
False
False
Receive Polarity Reverse
*3
• True
•
False
False
Elastic FIFO
*3
Use Elastic FIFO
*3
• True
*2
•
False
True
8b Mode
*3
• True
•
False
False
SKIP Mode
*3
• Disabled
• 802.3ae (one word)
• 802.3 (two words)
• PCIe
802.3ae (one word)
SKIP Word 0
*3
Text field to select user-defined
value
10’h283
UG028, July 1, 2014
89
- Speedster22i SerDes 1
- User Guide 1
- Table of Contents 2
- 4 UG028, July 1, 2014 4
- List of Figures 5
- List of Tables 6
- Overview 7
- Major standards supported 9
- 10 UG028, July 1, 2014 10
- SerDes Placement 11
- SerDes Architecture Overview 12
- 1. Common 13
- 3. Digital PMA (DPMA) 14
- PCS Self Test Logic 16
- 18 UG028, July 1, 2014 18
- Interface Encapsulation 20
- 8b/10b Encoder 20
- Running Disparity 20
- 22 UG028, July 1, 2014 22
- Polarity Bit Reversal (PBR) 23
- Symbol Alignment 23
- Modes of Operation 24
- Manual Mode: 24
- Bit Slip Mode: 24
- Automatic Mode: 24
- Deskew FIFO 25
- Functional Description 26
- Auto Mode: 26
- Symbol slip mode: 27
- 28 UG028, July 1, 2014 28
- EFIFO Operation 29
- 30 UG028, July 1, 2014 30
- 8b/10b Decoder 31
- Bit Slider 31
- PCS Self Test Checker 32
- PCS Interface 33
- PIPE Interface 34
- Clocking 36
- Debug and Test 38
- PMA loopback modes: 39
- PCS loopback modes: 39
- PMA Test Pattern Generator 40
- PMA Test Pattern Checker 40
- PCS Test Pattern Generator 40
- PRBS Generator 40
- PCS Test Pattern Checker 41
- Latency 42
- 44 UG028, July 1, 2014 44
- Configurations Supported 45
- 46 UG028, July 1, 2014 46
- 48 UG028, July 1, 2014 48
- Single-Lane Serdes Wrapper 50
- 52 UG028, July 1, 2014 52
- Overview Section: 53
- Entry field 54
- Purpose 54
- Available Options 54
- Choice made 54
- 56 UG028, July 1, 2014 56
- Section on PMA Settings: 57
- 58 UG028, July 1, 2014 58
- RX PMA Equalization 59
- RX PMA PLL 60
- TX PMA Driver 62
- TX PMA PLL 62
- Section on PCS Settings: 63
- RX PCS Settings 64
- RX PCS Symbol Alignment 66
- TX PCS Settings 68
- 70 UG028, July 1, 2014 70
- Files Generated by ACE-GUI 71
- Design and Wrapper Files 72
- Sequence 74
- 76 UG028, July 1, 2014 76
- Placement of SerDes 77
- Timing Constraints 78
- Design Guidelines 80
- Figure 37: Clock Region View 82
- 84 UG028, July 1, 2014 84
- Wide Bus 86
- Design Tips 87
- 88 UG028, July 1, 2014 88
- 90 UG028, July 1, 2014 90
- 92 UG028, July 1, 2014 92
- Design Bypassing PCS: 93
- Modification – 1 (ACE GUI): 94
- 96 UG028, July 1, 2014 96
- ACX_SERDES_SBUS_IF Module 99
- General signals: 100
- SerDes signals: 100
- Parallel Interface signals: 100
- UG028, July 1, 2014 101
- Pass-through signals: 102
- Loopback Modes 102
- SerDes signals 102
- Control signals 102
- SerDes Registers 103
- Electrical Specifications 104
- Transmitter 105
- 106 UG028, July 1, 2014 106
- Receiver 108
- Eye Diagram 110
- Reference Clock 112
- Revision History 113
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