Achronix Synthesis Bedienungsanleitung

UG018, April 15, 2013 1 Synthesis User Guide Using Synplify-Pro to target Speedster22i HD devices UG018 – April 15, 2013

10 UG018, April 15, 2013 honored:  Top-level output ports  Input pins of instantiated gates  Pins of inferred instances -freq Defines the f

UG018, April 15, 2013 11 During synthesis Synplify Pro will infer the BRAM80K block based on the above coding style.

12 UG018, April 15, 2013 Local Ram (LRAM) Distributed RAM or LRAM inferring or instantiation: Synplify-Pro is able to infer (or instantiate) LRAMs.

UG018, April 15, 2013 13 encoding. The FSM compiler can be disabled via the GUI or the from the Synplify project file with the following syntax: set_o

14 UG018, April 15, 2013 Figure 7- Replicated High Fan-in State Example Both state machines in the above Figure 7 are equivalent

UG018, April 15, 2013 15 Example Synplify-Pro Project File #-- Synopsys, Inc. #-- Version F-2011.09X Beta #-- Project file /home/testing_HD.prj #

16 UG018, April 15, 2013 # Compiler Options set_option -compiler_compatible 0 set_option -resource_sharing 0 # Compiler Options set_option -vhdl2

UG018, April 15, 2013 17 Revision History The following table shows the revision history for this document. Date Version Revisions 2/6/2012 1.0 Initi

2 UG018, April 15, 2013 Table of Contents Introduction ...

UG018, April 15, 2013 3 Synthesis User Guide Introduction This User Guide describes how to use Synplify Pro from Synopsys to synthesize a design and g

4 UG018, April 15, 2013 Synplify Pro Introduction We assume you have Synplify-Pro installed and the ‘synplify_pro’ command added to your $PATH. Thi

UG018, April 15, 2013 5 Select or click on the “New Project” button, then the following window will appear (shown in Figure 4): Figure

6 UG018, April 15, 2013 After adding the RTL files, the next step is to set the Implementation Options. By selecting this option the following wind

UG018, April 15, 2013 7 “Library Directories”. By default these two boxes are left empty. If user wants to add these paths, check the + switch and ad

8 UG018, April 15, 2013 Synthesis Optimization Recommendations There are several recommendations that can be implemented by the user during Synplif

UG018, April 15, 2013 9 Clock Constraints It is a requirement for the user to define all clocks with a specific duty cycle and frequency or clock per