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Special Functions ACX_SERIALIZE (Speedster22iHP Only)

Speedster Macro Cell Library

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ACX_SERIALIZE (Speedster22iHP Only)

N:1 Parallel-to-Serial Converter

d[input_width - 1 : 0]

ACX_DESERIALIZE

ACX_SERIALIZEimplementsanN:1parallel‐to‐seri alconversionofthedatainput,whereN

is specified by the input_width parameter.The serial output stream, q, is output atNtimes

faster than the frequency of clk. The serialization is performed starting from the least

significant bit and proceeding to the most s

ignificant bit. ACX_SERIALIZE may  be used to

rate multiply input data for higher processing rates inside the chip than is allowed at the 

devicepads. This block may be used in conjunction withACX_DESERIALIZE to perform a

deserializationofdatabeforeitisdrivenoffchipatlowerrates.

Table 8-3: Pin Description

Name Type Description

d[input_width –1 : 0] Data inputs.

clk Clock.

Data output. T

he value on the q output is the LSB to MSB seri-

alization of the parallel input data

d. The output data conver-

sion rate must be specified by the input_width parameter.

Table 8-4: Parameters

Parameter Defined Values Default Value

input_width

Note: TomakeoutputqN‐time

sfasterthanthefrequencyofclk,theuserneedstodrivealso

ACX_SERIALIZEblockclockportatN‐timesthefrequencyofclk.TocreateanN‐timesfasterclockof

theinputfrequencyclk,usercaninstantiateACX_VPLLmacro.

Verilog Instantiation Template

ACX_SERIALIZE #(.input_width(4))

instance_name(.q(user_q),

.d(user_d[input_width -1 : 0]),

.clk(N-times_faster_of_user_clk));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

Figure 8-2: Logic Symbol

input

output

positive integers 4

1 2 ... 198 199 200 201 202 203 204 205 206 207 208 ... 223 224

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Achronix Speedster22i User Macro Guide Bedienungsanleitung Seite 203