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Registers DFFS

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 81

DFFS

Positive Clock Edge D-Type Register with Asynchronous Set

DFFS

Figure 2-15: Logic Symbol

DFFSisasi

ngleD‐typeregisterwithdatainpu t(d),clock(ck), andactive‐lowset(sn)inputs

anddata(q)output.Theactive‐lowsetinputoverridesallotherinputswhenitisassertedlow

andsetsthedataoutputhigh.Iftheasynchronoussetinputisnotasserted,thedataoutputis

settotheva

lueonthedatainputuponthenextrisingedgeoftheclock.

Pins

Table 2-50: Pin Descriptions

Name Type Description

d Data input.

Active-low asynchronous set input. A lo

w on sn sets the q output high

independent of the other inputs.

ck Positive-edge clock input.

Data output. The value pr

esent on the data input is transferred to the q

output upon the rising edge of the clock if the asynchronous set input is

high.

Parameters

Table 2-51: Parameters

Parameter Defined Values Default Value

init 1’b1

sr_assertion “unclocked”

init

TheinitparameterdefinestheinitialvalueoftheoutputoftheDFFSregister.Thisisthevalue

theregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalueofthe

initparameteris1’b1.

sr_assertion

The sr_assertion param eter defines the behavior of the output when the sn set input is

asserted.Assigningthesr_assertionto“unclocked”resultsinanasychronousassertionofthe

reset signal, where the q output is set to one upon assertion of the active‐low reset signal.

Assigningthesr_assertionto“clocked”re

sultsinasynchronousassertionoftheresetsignal,

wheretheqoutputissettooneatthenextrisingedgeoftheclock.Thedefaultvalueofthe

sr_assertionparameteris“unclocked”.

input

output

1’b0, 1’b1

“unclocked”, “clocked”

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