
Speedster22i Macro Cell Library AchronixSemiconductorProprietary PAGE 49
Chapter 2 – Registers
Naming Convention
TheseMacrosarenamedbasedupontheircharacteristicsandbehavior.Ineachcase,thename
begins with DFF for D‐type Flip Flop. In addition to DFF each has one or more modifiers
whichindicatesit’suniqueproperties.
Themodifie
rsare:
E‐
Enable
N‐Negativ
elyClocked
R‐Reset(haspriorityov
erenable)
S‐Se
t(haspriorityoverenable)
C‐Clear(enabl
ehaspriority)
P‐Pre
set(enablehaspriority)
DFF
Positive Clock Edge D-Type Register
Figure 2-1: Logic Symbol
DFFisasi
ngleD‐typeregisterwithdatainput(d)andclock(ck)inputsanddata(q)output.
Thedataoutputissettothevalueonthedatainputuponthenextrisingedgeoftheclock.
Pins
Table 2-1: Pin Descriptions
Name Type Description
d Data input.
ck Positive-edge clock input.
q
Data output. T
he value present on the data input is transferred to the q out-
put upon the rising edge of the clock.
input
input
output
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