
Registers DFFNS
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 77
DFFNS
Negative Clock Edge D-Type Register with Asynchronous Set
Figure 2-13: Logic Symbol
DFFNS is a si
ngle D‐type register with data input (d), clock (ckn), and active‐low set (sn)
inputs and data (q) output. The active‐low set input overrides all other inputs when it is
assertedlowandsetsthedataoutputhigh.Iftheasynchronoussetinputisnotasserted,the
dataoutputissettotheva
lueonthedatainputuponthe nextfallingedgeoftheclock.
Pins
Table 2-42: Pin Descriptions
Name Type Description
d Data input.
sn
Active-low asynchronous set input. A lo
w on sn sets the q output high
independent of the other inputs.
ckn Negative-edge clock input.
q
Data output. The value pr
esent on the data input is transferred to the q
output upon the falling edge of the clock if the asynchronous set input is
high.
Parameters
Table 2-43: Parameters
Parameter Defined Values Default Value
init 1’b1
sr_assertion “unclocked”
init
The init parameter defines the initial value of the output of the DFFNS register.This isthe
valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue
oftheinitparameteris1’b1.
sr_assertion
The sr_assertion param eter defines the behavior of the output when the sn set input is
asserted.Assigningthesr_assertionto“unclocked”resultsinanasychronousassertionofthe
reset signal, where the q output is set to one upon assertion of the active‐low reset signal.
Assigningthesr_assertionto“clocked”re
sultsinasynchronousassertionoftheresetsignal,
wheretheqoutputissettooneatthenextrisingedgeoftheclock.Thedefaultvalueofthe
sr_assertionparameteris“unclocked”.
input
input
input
output
1’b0, 1’b1
“unclocked”, “clocked”
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