Achronix Speedster22i User Macro Guide Bedienungsanleitung Seite 88

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Registers DFFNES
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 72
DFFNES
Negative Clock Edge D-Type Register with Clock Enable and
Asynchronous/Synchronous Set
sn
ce
d
ckn
DFFNES
q
Figure 2-11: Logic Symbol
DFFNES is a si
ngle D type register with data input (d), clock enable (ce), clock (ckn), and
activelow set (sn) inputs and data (q) output. The activelow set inpu t overrides all other
inputswhenitis assertedlowand setsthedata output high.The resonseof theq outputin
re
sponsetotheassertedsetdependsonthevalueofthesr_assertionparameterandisdetailed
in Table 236
: DFFNES Function Table when sr_assertion = “unclocked” and Table
237: DFFNESFunctionTablewhensr_assertion=“clocked”.Ifth
esetinputisnotasserted,
thedataoutputissettoth
evalueonthedatainputuponthenextfallingedgeoftheclockif
theactivehighclockenableinputisasserted.
Pins
Table 2-34: Pin Descriptions
Name Type Description
d Data input.
sn
Active-low asynchronous/
synchronous set input. A low on sn sets the q
output high independent of the other inputs if the sr_assertion parameter
is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a low
on sn sets the q output high at the next falling edge of the clock.
ce Active-high clock enable input.
ckn Negative-edge clock input.
q
Data output. The value pr
esent on the data input is transferred to the q
output upon the falling edge of the clock if the clock enable input is high
and the set input is high.
Parameters
Table 2-35: Parameters
Parameter Defined Values Default Value
init 1’b1
sr_assertion “unclocked
init
TheinitparameterdefinestheinitialvalueoftheoutputoftheDFFNESregister.Thisisthe
valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue
oftheinitparameteris1’b1.
input
input
input
input
output
1’b0, 1’b1
unclocked, “clocked”
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