
Registers DFFNER
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 70
sr_assertion
The sr_assertion parameter defines the behavior of the output when the rn reset input is
asserted.Assigningthesr_assertionto“unclocked”resultsinanasychronousassertionofthe
reset signal, where the q output is set to zero upon assertion of the active‐low reset signal.
Assigningthesr_assertionto“clocked”re
sultsinasynchronousassertionoftheresetsignal,
wheretheqoutputissettozeroatthe nextfallingedgeoftheclock.Thedefaultvalueofthe
sr_assertionparameteris“unclocked”.
Table 2-32: DFFNER Function Table when sr_assertion = “unclocked”
Inputs Output
rn ce d ckn q
Table 2-33: DFFNER Function Table when sr_assertion = “clocked”
Inputs Output
rn ce d ckn q
Verilog Instantiation Template
DFFNER #(.init(1’b0),
.sr_assertion(“unclocked”))
instance_name
(.q(user_out),
.d(user_din),
.rn(user_reset),
.ce(user_clock_enable),
.ckn(user_clock));
0X X X 0
10 X XHold
11 0 0
11
1 1
0X X
0
10 X XHold
11 0 0
11
1 1
Kommentare zu diesen Handbüchern