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Registers DFFES

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 60

DFFES

Positive Clock Edge D-Type Register with Clock Enable and

Asynchronous/Synchronous Set

DFFES

Figure 2-6: Logic Symbol

DFFESisasi

ngleD‐typeregisterwithdatainput(d),clockenable(ce),clock(ck),andactive‐

low set (sn) inputs and data (q) output. The active‐low set input  overrides all other inputs

whenitisassertedlowandsetsthedataoutputhigh. Theresonseoftheqoutputinresponse

totheas

sertedsetdependsonthevalueofthesr_assertionparameterandisdetailedinTable

2‐19: DFFES Function Ta

ble when sr_assertion = “unclocked” and Table 2‐20: DFFES

FunctionTablewh

ensr_assertion=“clocked”.Ifthesetinputisnotasserted,thedataoutput

issettotheva

lueonthedatainputupon thenextrising edgeof  theclockifthe active‐high

clockenableinputisasserted.

Pins

Table 2-17: Pin Descriptions

Name Type Description

d Data input.

Active-low asynchronous/

synchronous set input. A low on sn sets the q

output high independent of the other inputs if the sr_assertion parameter

is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a low

on rn sets the q output high at the next rising edge of the clock.

ce Active-high clock enable input.

ck Positive-edge clock input.

Data output. The value pr

esent on the data input is transferred to the q

output upon the rising edge of the clock if the clock enable input is high

and the reset input is high.

Parameters

Table 2-18: Parameters

Parameter Defined Values Default Value

init 1’b1

sr_assertion “unclocked”

init

The init parameter defines the initial value of the output of the DFFES register.This is the

valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue

oftheinitparameteris1’b1.

input

output

1’b0, 1’b1

“unclocked”, “clocked”

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 223 224

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